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HIGH SPEED 2K x 8 DUAL PORT STATIC RAM
IDT7132SA/LA IDT7142SA/LA
Features
High-speed access - Commercial: 20/25/35/55/100ns (max.) - Industrial: 25ns (max.) - Military: 25/35/55/100ns (max.) Low-power operation - IDT7132/42SA Active: 325mW (typ.) Standby: 5mW (typ.) - IDT7132/42LA Active: 325mW (typ.) Standby: 1mW (typ.)

MASTER IDT7132 easily expands data bus width to 16-or-more bits using SLAVE IDT7142 On-chip port arbitration logic (IDT7132 only) BUSY output flag on IDT7132; BUSY input on IDT7142 Battery backup operation --2V data retention (LA only) TTL-compatible, single 5V 10% power supply Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC packages Military product compliant to MIL-PRF-38535 QML Industrial temperature range (-40C to +85C) is available for selected speeds
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/OOL-I/O7L
I/O Control
I/O Control
I/OOR-I/O7R
m
BUSYL(1,2) A10L A0L Address Decoder
11
BUSYR(1,2) MEMORY ARRAY
11
Address Decoder
A10R A0R
CEL OEL R/WL
ARBITRATION LOGIC
CER OER R/WR
2692 drw 01
NOTES: 1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270. IDT7142 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270.
JUNE 2004
1
(c)2004 Integrated Device Technology, Inc. DSC-2692/16
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7142 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 16-or-more-bit memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and l/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA) versions offer battery backup data retention capability, with each DualPort typically consuming 200W from a 2V battery. The IDT7132/7142 devices are packaged in a 48-pin sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
CEL R/WL BUSYL A10L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 48 2 47 3 46 4 45 5 44 6 43 7 IDT7132/ 42 8 7142 41 9 P or C 40 10 39 11 P48-1(4) 38 12 37 & 13 C48-2(4) 36 14 35 15 48-Pin 34 16 DIP 33 17 Top 32 18 View(5) 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC CER R/WR BUSYR A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R
2692 drw 02
R/WR BUSYR A10R
BUSYL R/WL CEL
A0L OEL A10L
INDEX
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L
654 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
48 47 46 45 44 43 42 41 40 39 IDT7132/42L48 or F L48-1(4) 38 & 37 (4) F48-1 36 48-Pin LCC/ Flatpack (5) 35 Top View 34 33 32 31 22 23 24 25 26 27 28 29 30 1
32
VCC CER
OER
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R
,
,
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. P48-1 package body is approximately .55 in x 2.43 in x .18 in. C48-2 package body is approximately .62 in x 2.43 in x .15 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Capacitance(1)
Symbol CIN COUT
I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV
2692 drw 03
(TA = +25C,f = 1.0MHz)
Max. 11 11 Unit pF pF
2692 tbl 00
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 3V to 0V.
2
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
INDEX
76 54 32 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20
1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R
2692 drw 04
IDT7132/42J J52-1(4) 52-Pin PLCC Top View(5)
21 22 23 24 25 26 27 28 29 30 31 32 33
I/O4L I/O5L I/O6L I/O7L N/C GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
Military -0.5 to +7.0 Unit V
Military Grade
NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0
Recommended Operating Temperature and Supply Voltage(1,2)
Ambient Temperature -55 C to+125 C
O O
R/WR BUSYR N/C A10R
A0L OEL A10L N/C BUSYL
Pin Configurations(1,2,3) (con't.)
R/WL CEL VCC CER
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2692 tbl 02
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
-65 to +135 -65 to +150 50
o
C C
Commercial Industrial
0 C to +70 C
O O
-40 C to +85 C
O O
o
mA
2692 tbl 01
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(2)
Unit V V V V
2692 tbl 03
0.8
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
3 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5,8) (VCC = 5.0V 10%)
7132X20(2) 7142X20(2) Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CEL = CER = VIL, Outputs Disabled f = fMAX(3) Version COM'L MIL & IND COM'L MIL & IND CE"A" = VIL and CE"B" = VIH(6) Active Port Outputs Disabled f=fMAX(3) COM'L MIL & IND COM'L MIL & IND CE"A" < 0.2V andCE"B" > VCC -0.2V(6) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L MIL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 110 110
____ ____
7132X25(7) 7142X25(7) Com'l, Ind & Military Typ. 110 110 110 110 30 30 30 30 65 65 65 65 1.0 0.2 1.0 0.2 60 60 60 60 Max. 220 170 280 220 65 45 80 60 150 115 160 125 15 5 30 10 145 105 155 115
7132X35 7142X35 Com'l & Military Typ. 80 80 80 80 25 25 25 25 50 50 50 50 1.0 0.2 1.0 0.2 45 45 45 45 Max. 165 120 230 170 65 45 80 60 125 90 150 115 15 4 30 10 110 85 145 105
2692 tbl 04a
Max. 250 200
____ ____
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CEL = CER = VIH, f = fMAX(3)
30 30
____ ____
65 45
____ ____
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
65 65
____ ____
165 125
____ ____
mA
ISB3
Full Standby Current (Both Ports - All CMOS Level Inputs)
CEL and CER > VCC -0.2V VIN > VCC -0.2V or VIN < 0.2V, f = 0(4)
1.0 0.2
____ ____
15 5
____ ____
mA
ISB4
Full Standby Current (One Port - All CMOS Level Inputs)
60 60
____ ____
155 115
____ ____
mA
7132X55 7142X55 Com'l & Military Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) CEL = CER = VIL, Outputs Disabled f = fMAX(3) Test Condition Version COM'L MIL & IND COM'L MIL & IND CE"A" = VIL and CE"B" = VIH(6) Active Port Outputs Disabled f=fMAX(3) COM'L MIL & IND COM'L MIL & IND CE"A" < 0.2V and CE"B" > VCC -0.2V(6) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L MIL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ. 65 65 65 65 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 Max. 155 110 190 140 65 35 65 45 110 75 125 90 15 4 30 10 100 70 110 85
7132X100 7142X100 Com'l & Military Typ. 65 65 65 65 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 Max. 155 110 190 140 55 35 65 45 110 75 125 90 15 4 30 10 95 70 110 80
2692 tbl 04b
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CEL = CER = VIH, f = fMAX(3)
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
mA
ISB3
Full Standby Current (Both Ports - All CMOS Level Inputs)
CEL and CER > VCC -0.2V VIN > VCC -0.2V or VIN < 0.2V, f = 0(4)
mA
ISB4
Full Standby Current (One Port - All CMOS Level Inputs)
mA
NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. PLCC Package only 3. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vcc = 5V, TA=+25C for Typ and is not production tested. Vcc DC = 100mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port "A". 7. Not available in DIP packages. 8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
4
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V 10%)
7132SA 7142SA Symbol |ILI| |ILO| VOL VOL VOH Parameter Input Leakage Current
(1)
7132LA 7142LA Min.
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC VCC = 5.5V, CE = VIH, VOUT = 0V to VCC IOL = 4mA IOL = 16mA IOH = -4mA
Min.
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit A
Output Leakage Current Output Low Voltage Open Drain Output Low Voltage (BUSY) Output High Voltage
___
___
A V V V
2692 tbl 05
___ ___
___ ___
2.4
2.4
NOTE: 1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2.0V CE > VCC -0.2V VIN > VCC -0.2V or tCDR(3) tR(3) Chip Deselect to Data Retention Time Operation Recovery Time VIN < 0.2V Mil. & Ind. Com'l. Test Condition Min. 2.0
___ ___
Typ.(1)
___
Max.
___
Unit V A A ns ns
2692 tbl 06
100 100
___ ___
4000 1500
___ ___
0 tRC(2)
NOTES: 1. VCC = 2V, TA = +25C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE VDR 2.0V
VCC
4.5V tCDR
4.5V tR
CE VIH
VDR VIH
2692 drw 05 ,
5 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1, 2, and 3
2692 tbl 07
5V 1250 DATAOUT 775 30pF*
*100pF for 55 and 100ns versions
5V 1250 DATAOUT 775 5pF*
,
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW) * Including scope and jig
5V 270 BUSY 30pF*
*100pF for 55 and 100ns versions 2692 drw 06
Figure 3. BUSY AC Output Test Load
6
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3,5)
7132X20(2) 7142X20(2) Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,4) (1,4) (4) (4)
7132X25(2) 7142X25(2) Com'l, Ind & Military Min. Max.
7132X35 7142X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20
____ ____ ____
____
25
____ ____ ____
____
35
____ ____ ____
____
ns ns ns ns ns ns ns ns ns
2692 tbl 08a
20 20 11
____ ____
25 25 12
____ ____
35 35 20
____ ____
3 0
____
3 0
____
3 0
____
Output High-Z Time
10
____
10
____
15
____
Chip Enable to Power Up Time
0
____
0
____
0
____
Chip Disable to Power Down Time
20
25
35
7132X55 7142X55 Com'l & Military Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,4) Output High-Z Time
(1,4) (4)
7132X100 7142X100 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
55
____ ____ ____
____
100
____ ____ ____
____
ns ns ns ns ns ns ns ns ns
2692 tbl 08b
55 55 25
____ ____
100 100 40
____ ____
3 5
____
10 5
____
25
____
40
____
Chip Enable to Power Up Time
0
____
0
____
Chip Disable to Power Down Time(4)
50
50
NOTES: 1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2). 2. PLCC package only. 3. 'X' in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. 5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC ADDRESS tAA tOH DATAOUT BUSYOUT tBDDH(2,3)
2692 drw 07
tOH DATA VALID
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 2, Either Side(1)
tACE CE tAOE(3) OE tLZ(4) DATAOUT tLZ ICC CURRENT ISS tPU 50%
(4)
tHZ(5)
tHZ(5) VALID DATA tPD(3) 50%
2692 drw 08
NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. 4. Timing depends on which signal is asserted last, OE or CE. 5. Timing depends on which signal is de-asserted first, OE or CE.
8
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(5,6)
7132X20(2) 7142X20(2) Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (3) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width(4) Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write
(1) (1)
7132X25(2) 7142X25(2) Com'l, Ind & Military Min. Max.
7132X35 7142X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20 15 15 0 15 0 10
____
____ ____ ____ ____ ____ ____ ____
25 20 20 0 15 0 12
____
____ ____ ____ ____ ____ ____ ____
35 30 30 0 25 0 15
____
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns
2692 tbl 09
10
____
10
____
15
____
0
____
0
____
0
____
10
____
10
____
15
____
(1)
0
0
0
7132X55 7142X55 Com'l & Military Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (3) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width
(4)
7132X100 7142X100 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
55 40 40 0 30 0 20
____
____ ____ ____ ____ ____ ____ ____
100 90 90 0 55 0 40
____
____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns
2692 tbl 10
Write Recovery Time Data Valid to End-of-Write Output High-Z Time (1) Data Hold Time Write Enable to Output in High-Z(1) Output Active from End-of-Write
(1)
25
____
40
____
0
____
0
____
30
____
40
____
0
0
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. PLCC package only. 3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. 'X' in part numbers indicates power rating (SA or LA). 6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
9 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC ADDRESS tHZ(7) OE tAW CE tAS(6) R/W tWZ(7) DATA OUT
(4)
tWP(2)
tWR(3)
tHZ(7)
tOW
(4)
tDW DATA IN
tDH
2692 drw 09
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC ADDRESS tAW CE tAS(6) R/W tDW DATA IN
2692 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
tEW(2)
tWR(3)
tDH
10
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(7,8)
7132X20(1) 7142X20(1) Com'l Only Symbol BUSY Timing (For Master IDT7132 Only) tBAA tBDA tBAC tBDC tWDD tWH tDDD tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay (2) Write Hold After BUSY
(6) (2)
____ ____ ____ ____ ____
7132X25(2) 7142X25(2) Com'l, Ind & Military Min. Max.
7132X35 7142X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20 20 20 20 50
____
____ ____ ____ ____ ____
20 20 20 20 50
____
____ ____ ____ ____ ____
20 20 20 20 60
____
ns ns ns ns ns ns ns ns ns
12
____
15
____
20
____
Write Data Valid to Read Data Delay Arbitration Priority Set-up Time (3) BUSY Disable to Valid Data
(4)
35
____
35
____
35
____
5
____
5
____
5
____
25
35
35
BUSY Timing (For Slave IDT7142 Only) tWB tWH tWDD tDDD Write to BUSY Input(5) Write Hold After BUSY
(6)
0 12
____ ____
____ ____
0 15
____ ____
____ ____
0 20
____ ____
____ ____
ns ns ns ns
2692 tbl 11a
Write Pulse to Data Delay (2) Write Data Valid to Read Data Delay (2)
40 30
50 35
60 35
7132X55 7142X55 Com'l & Military Symbol BUSY Timing (For Master IDT7132 Only) tBAA tBDA tBAC tBDC tWDD tWH tDDD tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay Write Hold After BUSY
(6) (2)
____ ____ ____ ____ ____
7132X100 7142X100 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
30 30 30 30 80
____
____ ____ ____ ____ ____
50 50 50 50 120
____
ns ns ns ns ns ns ns ns ns
20
____
20
____
Write Data Valid to Read Data Delay (2) Arbitration Priority Set-up Time (3) BUSY Disable to Valid Data
(4)
55
____
100
____
5
____
5
____
50
65
BUSY Timing (For Slave IDT7142 Only) tWB tWH tWDD tDDD Write to BUSY Input(5) Write Hold After BUSY(6) Write Pulse to Data Delay
(2) (2)
0 20
____ ____
____ ____
0 20
____ ____
____ ____
ns ns ns ns
2692 tbl 11b
80 55
120 100
Write Data Valid to Read Data Delay
NOTES: 1. PLCC package only. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to "Timing Waveform of Write with Port -to-Port Read and BUSY." 3. To ensure that the earlier of the two ports wins. 4. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 5. To ensure that a write cycle is inhibited on port "B" during contention on port "A". 6. To ensure that a write cycle is completed on port "B" after contention on port "A". 7. 'X' in part numbers indicates power rating (SA or LA). 8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
11 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN"A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT"B" tDDD
NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
2692 drw 11 (1)
tDH
VALID
MATCH t BDA tBDD
VALID
Timing Waveform of Write with BUSY(4)
tWP R/W"A" tWB(3) BUSY"B" tWH(1) R/W"B"
(2)
,
2692 drw 12
NOTES: 1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB applies only to the slave version (IDT7142). 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
12
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
"A"
and "B" CE"B" tAPS(2) CE"A" tBAC
ADDRESSES MATCH
tBDC
BUSY"A"
2692 drw 13
Timing Waveform of BUSY Arbitration Controlled by Address Match Timing(1)
tRC or tWC ADDR"A" tAPS ADDR"B" tBAA BUSY"B"
2692 drw 14 (2)
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
tBDA
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
Truth Tables Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1) R/W X X L H X CE H H L L L OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Disabled and in Power-Down Mode, ISB2 or ISB4 CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 Data on Port Written into Memory (2) Data in Memory Output on Port(3) High Impedance Outputs
2692 tbl 12
NOTES: 1. A0L - A10L A0R - A10R 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = HIGH IMPEDANCE
13 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Table II -- Address BUSY Arbitration
Inputs CEL X H X L CER X X H L AOL-A10L AOR-A10R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
2692 tbl 13
The BUSY outputs on the IDT7132 RAM master are totem-pole type outputs and do not require pull-up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate.
Width Expansion with Busy Logic Master/Slave Arrays
NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT7132 (master). Both are inputs for IDT7142 (slave). BUSYX outputs on the IDT7132 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
When expanding an SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7132/ IDT7142 SRAMs the BUSY pin is an output if the part is Master (IDT7132), and the BUSY pin is an input if the part is a Slave (IDT7142) as shown in Figure 3.
5V 270
MASTER Dual Port SRAM BUSYL
CE BUSYR
SLAVE Dual Port SRAM BUSYL
CE BUSYR
DECODER
5V 270
The IDT7132/IDT7142 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7132/IDT7142 has an automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted.
Functional Description
MASTER Dual Port SRAM BUSYL BUSYL
CE BUSYR
SLAVE Dual Port SRAM BUSYL
CE BUSYR BUSYR
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY Logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation.
Busy Logic
If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
14
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT A XXXX 999 A Device Type Power Speed Package A Process/ Temperature Range BLANK Commercial (0C to +70C) Industrial (-40C to +85C) I(1) Military (-55C to +125C) B Compliant to MIL-PRF-38535 QML P C J L48 F 20 25 35 55 100 48-pin Plastic DIP (P48-1) 48-pin Sidebraze DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) Commercial PLCC Only Commercial, Industrial & Military Commercial & Military Commercial & Military Commercial & Military
Speed in nanoseconds
,
LA SA 7132 7142
NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
Low Power Standard Power 16K (2K x 8-Bit) MASTER Dual-Port RAM 16K (2K x 8-Bit) SLAVE Dual-Port RAM
2692 drw 16
Datasheet Document History
03/24/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Page 14 Changed Busy Logic and Width Expansion copy Replaced IDT logo Pages 1 and 2 Moved full "Description" to page 2 and adjusted page layouts Page 1 Added "(LAonly)" to paragraph Page 2 Fixed P48-1 body package description Page 3 Increased storage temperature parameters Clarified TA parameter Page 4 DC Electrical parameters-changed wording from "open" to "disabled" Page 6 Added asteriks to Figures 1 and 3 in drw 06 Page 14 Corrected part numbers Changed 500mV to 0mV in notes Datasheet Document History continued on page 16
06/08/99: 08/26/99: 11/10/99: 01/12/00:
15 6.42
IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
06/11/04: Page 6 Corrected errors in Figure 3 by changing 1250 to 270 and removing "or Int" and Int Page 4, 7, 9, 11 & 15 Clarified Industrial temp offering for 25ns Page 5 Removed INT from VOL parameter in DC Electrical Characteristics table Page 6 Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns
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16

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